Publication: Concurrent Error Detection in Finite Field Arithmetic Operations Using Pipelined and Systolic Architectures

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Title	Concurrent Error Detection in Finite Field Arithmetic Operations Using Pipelined and Systolic Architectures
Authors/Editors*	S. Bayat-Sarmadi and M. A. Hasan
Where published*	CACR, Univ. of Waterloo
How published*	Technical Report
Year*	2007
Volume
Number	2007-30
Pages
Publisher
Keywords
Link	http://www.cacr.math.uwaterloo.ca/
Abstract	In this work we consider mainly detection of errors in polynomial, dual and normal bases arithmetic operations. Error detection is performed by recomputing with shifted operands method while the operation unit is in use. This scheme is efficient for pipelined architectures, particularly systolic arrays. Additionally, One semi-systolic multiplier for each of the polynomial, dual, type I and type II optimal normal bases is presented in this work. The results show that having better or similar space and time overheads compared to a number of related previous work, the multipliers have generally a high error detection capability, e.g., the error detection capability of the scheme for the single and multiple stuck-at faults in a polynomial basis multiplier are 99.08% and 100%, respectively. Finally, we also comments on how RESO can be used for concurrent error correction to deal with transient faults.